SOI Wafers

Short Description:

The SOI wafer is a sandwich-like structure with three layers; Including the top layer (device layer), the middle of the buried oxygen layer (for the insulating SiO2 layer) and the bottom substrate (bulk silicon). SOI wafers are produced using the SIMOX method and wafer bonding technology, which allows for thinner and more accurate device layers, uniform thickness and low defect density.

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Product Detail

Product Tags

SOI Wafers(1)

Application field

1. High-speed integrated circuit

2. Microwave devices

3. High temperature integrated circuit

4. Power devices

5. Low power integrated circuit

6. MEMS

7. Low voltage integrated circuit

Item		Argument
Overall	Wafer Diameter 晶圆尺寸(mm)	50/75/100/125/150/200mm±25um
	Bow/Warp 翘曲度(<um)	<10um
	Particles 颗粒度(<ea)	0.3um<30ea
	Flats/Notch 定位边/定位槽	Flat or Notch
	Edge Exclusion 边缘去除(mm)	/
Device Layer 器件层	Device-layer Type/Dopant 器件层掺杂类型	N-Type/P-Type B/ P/ Sb / As
	Device-layer Orientation 器件层晶向	<1-0-0> / <1-1-1> / <1-1-0>
	Device-layer Thickness 器件层厚度(um)	0.1~300um
	Device-layer Resistivity 器件层电阻率(ohm•cm)	0.001~100,000 ohm-cm
	Device-layer Particles 器件层颗粒度(<ea)	<30ea@0.3
	Device Layer TTV 器件层TTV(<um)	<10um
	Device Layer Finish 器件层表面处理	Polished
BOX	Buried Thermal Oxide Thickness 埋氧层厚度(um)	50nm(500Å)~15um
Handle Layer 衬底	Handle Wafer Type/Dopant 衬底层类型	N-Type/P-Type B/ P/ Sb / As
	Handle Wafer Orientation 衬底晶向	<1-0-0> / <1-1-1> / <1-1-0>
	Handle Wafer Resistivity 衬底电阻率(ohm•cm)	0.001~100,000 ohm-cm
	Handle Wafer Thickness 衬底厚度(um)	>100um
	Handle Wafer Finish 衬底表面处理	Polished
SOI wafers of target specifications can be customized according to customer requirements.