Semicera’s SOI Wafer (Silicon On Insulator) is designed to deliver superior electrical isolation and thermal performance. This innovative wafer structure, featuring a silicon layer on an insulating layer, ensures enhanced device performance and reduced power consumption, making it ideal for a variety of high-tech applications.
Our SOI wafers offer exceptional benefits for integrated circuits by minimizing parasitic capacitance and improving device speed and efficiency. This is crucial for modern electronics, where high performance and energy efficiency are essential for both consumer and industrial applications.
Semicera employs advanced manufacturing techniques to produce SOI wafers with consistent quality and reliability. These wafers provide excellent thermal insulation, making them suitable for use in environments where heat dissipation is a concern, such as in high-density electronic devices and power management systems.
The use of SOI wafers in semiconductor fabrication allows for the development of smaller, faster, and more reliable chips. Semicera’s commitment to precision engineering ensures that our SOI wafers meet the high standards required for cutting-edge technologies in fields like telecommunications, automotive, and consumer electronics.
Choosing Semicera’s SOI Wafer means investing in a product that supports the advancement of electronic and microelectronic technologies. Our wafers are designed to provide enhanced performance and durability, contributing to the success of your high-tech projects and ensuring that you stay at the forefront of innovation.
Items |
Production |
Research |
Dummy |
Crystal Parameters |
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Polytype |
4H |
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Surface orientation error |
<11-20 >4±0.15° |
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Electrical Parameters |
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Dopant |
n-type Nitrogen |
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Resistivity |
0.015-0.025ohm·cm |
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Mechanical Parameters |
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Diameter |
150.0±0.2mm |
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Thickness |
350±25 μm |
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Primary flat orientation |
[1-100]±5° |
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Primary flat length |
47.5±1.5mm |
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Secondary flat |
None |
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TTV |
≤5 μm |
≤10 μm |
≤15 μm |
LTV |
≤3 μm(5mm*5mm) |
≤5 μm(5mm*5mm) |
≤10 μm(5mm*5mm) |
Bow |
-15μm ~ 15μm |
-35μm ~ 35μm |
-45μm ~ 45μm |
Warp |
≤35 μm |
≤45 μm |
≤55 μm |
Front(Si-face) roughness(AFM) |
Ra≤0.2nm (5μm*5μm) |
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Structure |
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Micropipe density |
<1 ea/cm2 |
<10 ea/cm2 |
<15 ea/cm2 |
Metal impurities |
≤5E10atoms/cm2 |
NA |
|
BPD |
≤1500 ea/cm2 |
≤3000 ea/cm2 |
NA |
TSD |
≤500 ea/cm2 |
≤1000 ea/cm2 |
NA |
Front Quality |
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Front |
Si |
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Surface finish |
Si-face CMP |
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Particles |
≤60ea/wafer (size≥0.3μm) |
NA |
|
Scratches |
≤5ea/mm. Cumulative length ≤Diameter |
Cumulative length≤2*Diameter |
NA |
Orange peel/pits/stains/striations/ cracks/contamination |
None |
NA |
|
Edge chips/indents/fracture/hex plates |
None |
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Polytype areas |
None |
Cumulative area≤20% |
Cumulative area≤30% |
Front laser marking |
None |
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Back Quality |
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Back finish |
C-face CMP |
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Scratches |
≤5ea/mm,Cumulative length≤2*Diameter |
NA |
|
Back defects (edge chips/indents) |
None |
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Back roughness |
Ra≤0.2nm (5μm*5μm) |
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Back laser marking |
1 mm (from top edge) |
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Edge |
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Edge |
Chamfer |
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Packaging |
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Packaging |
Epi-ready with vacuum packaging Multi-wafer cassette packaging |
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*Notes: "NA" means no request Items not mentioned may refer to SEMI-STD. |