Semicera’s Silicon On Insulator (SOI) Wafer is at the forefront of semiconductor innovation, offering enhanced electrical isolation and superior thermal performance. The SOI structure, consisting of a thin silicon layer on an insulating substrate, provides critical benefits for high-performance electronic devices.
Our SOI wafers are designed to minimize parasitic capacitance and leakage currents, which is essential for developing high-speed and low-power integrated circuits. This advanced technology ensures that devices operate more efficiently, with improved speed and reduced energy consumption, crucial for modern electronics.
The advanced manufacturing processes employed by Semicera guarantee the production of SOI wafers with excellent uniformity and consistency. This quality is vital for applications in telecommunications, automotive, and consumer electronics, where reliable and high-performing components are required.
In addition to their electrical benefits, Semicera’s SOI wafers offer superior thermal insulation, enhancing heat dissipation and stability in high-density and high-power devices. This feature is particularly valuable in applications that involve significant heat generation and require effective thermal management.
By choosing Semicera’s Silicon On Insulator Wafer, you invest in a product that supports the advancement of cutting-edge technologies. Our commitment to quality and innovation ensures that our SOI wafers meet the rigorous demands of today’s semiconductor industry, providing the foundation for next-generation electronic devices.
Items |
Production |
Research |
Dummy |
Crystal Parameters |
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Polytype |
4H |
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Surface orientation error |
<11-20 >4±0.15° |
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Electrical Parameters |
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Dopant |
n-type Nitrogen |
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Resistivity |
0.015-0.025ohm·cm |
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Mechanical Parameters |
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Diameter |
150.0±0.2mm |
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Thickness |
350±25 μm |
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Primary flat orientation |
[1-100]±5° |
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Primary flat length |
47.5±1.5mm |
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Secondary flat |
None |
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TTV |
≤5 μm |
≤10 μm |
≤15 μm |
LTV |
≤3 μm(5mm*5mm) |
≤5 μm(5mm*5mm) |
≤10 μm(5mm*5mm) |
Bow |
-15μm ~ 15μm |
-35μm ~ 35μm |
-45μm ~ 45μm |
Warp |
≤35 μm |
≤45 μm |
≤55 μm |
Front(Si-face) roughness(AFM) |
Ra≤0.2nm (5μm*5μm) |
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Structure |
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Micropipe density |
<1 ea/cm2 |
<10 ea/cm2 |
<15 ea/cm2 |
Metal impurities |
≤5E10atoms/cm2 |
NA |
|
BPD |
≤1500 ea/cm2 |
≤3000 ea/cm2 |
NA |
TSD |
≤500 ea/cm2 |
≤1000 ea/cm2 |
NA |
Front Quality |
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Front |
Si |
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Surface finish |
Si-face CMP |
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Particles |
≤60ea/wafer (size≥0.3μm) |
NA |
|
Scratches |
≤5ea/mm. Cumulative length ≤Diameter |
Cumulative length≤2*Diameter |
NA |
Orange peel/pits/stains/striations/ cracks/contamination |
None |
NA |
|
Edge chips/indents/fracture/hex plates |
None |
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Polytype areas |
None |
Cumulative area≤20% |
Cumulative area≤30% |
Front laser marking |
None |
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Back Quality |
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Back finish |
C-face CMP |
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Scratches |
≤5ea/mm,Cumulative length≤2*Diameter |
NA |
|
Back defects (edge chips/indents) |
None |
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Back roughness |
Ra≤0.2nm (5μm*5μm) |
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Back laser marking |
1 mm (from top edge) |
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Edge |
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Edge |
Chamfer |
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Packaging |
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Packaging |
Epi-ready with vacuum packaging Multi-wafer cassette packaging |
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*Notes: "NA" means no request Items not mentioned may refer to SEMI-STD. |