Si Epitaxy

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Si Epitaxy – Achieve superior device performance with Semicera’s Si Epitaxy, offering precision-grown silicon layers for advanced semiconductor applications.


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Semicera introduces its high-quality Si Epitaxy services, designed to meet the exacting standards of today’s semiconductor industry. Epitaxial silicon layers are critical for the performance and reliability of electronic devices, and our Si Epitaxy solutions ensure that your components achieve optimal functionality.

Precision-Grown Silicon Layers Semicera understands that the foundation of high-performance devices lies in the quality of the materials used. Our Si Epitaxy process is meticulously controlled to produce silicon layers with exceptional uniformity and crystal integrity. These layers are essential for applications ranging from microelectronics to advanced power devices, where consistency and reliability are paramount.

Optimized for Device Performance The Si Epitaxy services offered by Semicera are tailored to enhance the electrical properties of your devices. By growing high-purity silicon layers with low defect densities, we ensure that your components perform at their best, with improved carrier mobility and minimized electrical resistivity. This optimization is critical for achieving the high-speed and high-efficiency characteristics demanded by modern technology.

Versatility in Applications Semicera’s Si Epitaxy is suitable for a wide range of applications, including the production of CMOS transistors, power MOSFETs, and bipolar junction transistors. Our flexible process allows for customization based on the specific requirements of your project, whether you need thin layers for high-frequency applications or thicker layers for power devices.

Superior Material Quality Quality is at the heart of everything we do at Semicera. Our Si Epitaxy process uses state-of-the-art equipment and techniques to ensure that each silicon layer meets the highest standards of purity and structural integrity. This attention to detail minimizes the occurrence of defects that could impact device performance, resulting in more reliable and longer-lasting components.

Commitment to Innovation Semicera is committed to staying at the forefront of semiconductor technology. Our Si Epitaxy services reflect this commitment, incorporating the latest advancements in epitaxial growth techniques. We continuously refine our processes to deliver silicon layers that meet the evolving needs of the industry, ensuring that your products remain competitive in the market.

Tailored Solutions for Your Needs Understanding that every project is unique, Semicera offers customized Si Epitaxy solutions to match your specific needs. Whether you require particular doping profiles, layer thicknesses, or surface finishes, our team works closely with you to deliver a product that meets your precise specifications.

Items

Production

Research

Dummy

Crystal Parameters

Polytype

4H

Surface orientation error

<11-20 >4±0.15°

Electrical Parameters

Dopant

n-type Nitrogen

Resistivity

0.015-0.025ohm·cm

Mechanical Parameters

Diameter

150.0±0.2mm

Thickness

350±25 μm

Primary flat orientation

[1-100]±5°

Primary flat length

47.5±1.5mm

Secondary flat

None

TTV

≤5 μm

≤10 μm

≤15 μm

LTV

≤3 μm(5mm*5mm)

≤5 μm(5mm*5mm)

≤10 μm(5mm*5mm)

Bow

-15μm ~ 15μm

-35μm ~ 35μm

-45μm ~ 45μm

Warp

≤35 μm

≤45 μm

≤55 μm

Front(Si-face) roughness(AFM)

Ra≤0.2nm (5μm*5μm)

Structure

Micropipe density

<1 ea/cm2

<10 ea/cm2

<15 ea/cm2

Metal impurities

≤5E10atoms/cm2

NA

BPD

≤1500 ea/cm2

≤3000 ea/cm2

NA

TSD

≤500 ea/cm2

≤1000 ea/cm2

NA

Front Quality

Front

Si

Surface finish

Si-face CMP

Particles

≤60ea/wafer (size≥0.3μm)

NA

Scratches

≤5ea/mm. Cumulative length ≤Diameter

Cumulative length≤2*Diameter

NA

Orange peel/pits/stains/striations/ cracks/contamination

None

NA

Edge chips/indents/fracture/hex plates

None

Polytype areas

None

Cumulative area≤20%

Cumulative area≤30%

Front laser marking

None

Back Quality

Back finish

C-face CMP

Scratches

≤5ea/mm,Cumulative length≤2*Diameter

NA

Back defects (edge chips/indents)

None

Back roughness

Ra≤0.2nm (5μm*5μm)

Back laser marking

1 mm (from top edge)

Edge

Edge

Chamfer

Packaging

Packaging

Epi-ready with vacuum packaging

Multi-wafer cassette packaging

*Notes: "NA" means no request Items not mentioned may refer to SEMI-STD.

tech_1_2_size
SiC wafers

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